A flash memory device known as a flash EEPROM, in general, includes a memory cell array of memory cells each of which consists of a floating gate transistor. The memory cell array includes strings (or NAND strings) of floating gate transistors. In each string, the floating gate transistors are connected in series between a string select transistor and a ground select transistor. A plurality of word lines are arranged to intersect NAND strings and are connected to corresponding floating gate transistors of each NAND string, respectively.
Floating gate transistors, that is, memory cells, are erased to have a threshold voltage (e.g., −1V to −3V) that is lower than 0V. In order to program a selected memory cell, a high voltage (e.g., 20V) is applied to a word line of the selected memory cell during a given period of time. This causes the threshold voltage of the selected memory cell to shift into a higher level. During a program operation, the threshold voltages of unselected memory cells are not changed.
A problem arises when memory cells connected to a common word line are programmed. When a program voltage is applied to a word line, it is applied not only to selected memory cells but also to unselected memory cells. The selected and unselected memory cells are connected to the same word line. In this bias condition, the unselected memory cells connected to the word line can become programmed. Unintended programming of unselected memory cells is referred to as “program disturb”.
One of the techniques for preventing a program disturb phenomenon is a program inhibiting method referred to as a self-boosting scheme. The program inhibiting method using the self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN” and U.S. Pat. No. 5,991,202 entitled “METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORY”, which are incorporated herein by reference.
In the program inhibiting method using the self-boosting scheme, a ground path is shut off by applying a voltage of 0V to a gate of a ground select transistor. A voltage of 0V is applied to a selected bit line, and a power supply voltage as a program inhibition voltage is applied to an unselected bit line. At the same time, a voltage (a power supply voltage or a voltage lower than the power supply voltage) is applied to a gate of a string select transistor. This causes the source of the string select transistor to be charged up to a voltage of (Vcc-Vth) (where Vth is the threshold voltage of the string select transistor). At this time, the string select transistor is shut off. A channel voltage of a program-inhibited cell transistor is boosted by applying a program voltage Vpgm to a selected word line and a pass voltage Vpass to unselected word lines. The pass voltage Vpass is higher than a power supply voltage and lower than the program voltage Vpgm. With these bias conditions, F-N tunneling does not occur between the floating gate and the channel. Accordingly, the program-inhibited cell transistor is maintained in an erased state.
Another technique for preventing the program disturb is a program inhibiting method using a local self-booting technique. The program inhibiting method using the local self-booting technique is disclosed in U.S. Pat. No. 5,715,194 entitled “BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY” and U.S. Pat. No. 6,061,270 entitled “METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL”, which are incorporated herein by reference.
In the program inhibiting method using the local self-boosting scheme, a voltage of 0V is applied to two unselected word lines adjacent to a selected word line. After a pass voltage Vpass is applied to remaining unselected word lines, a program voltage Vpgm is applied to a selected word line. By this biasing scheme, a channel of a local self-boosted cell transistor is limited to a selected word line, and a channel boosting voltage of a program-inhibited cell transistor is increased as compared with the program inhibiting method using the self-boosting scheme. Therefore, no F-N tunneling arises between a floating gate of the program-inhibited cell transistor and a channel, so that the program-inhibited cell transistor is retained in an erased state. In the local self-boosting scheme, a voltage of 0V can be applied to either one of two unselected word lines adjacent to a selected word line.
The above-described program methods have associated with them the following problem. As the degree of integration of a flash memory device is gradually increased, the interval between word lines narrows. Although the interval between word lines narrows, voltages to word lines are not varied. In other words, although the interval between word lines narrows, a program voltage applied to a selected word line and a pass voltage applied to unselected word lines are maintained without variation. For this reason, as the interval between word lines increasingly narrows, the dielectric layer between a selected word line and an unselected word line can become broken down due to a high voltage difference between word lines. For example, in the case that an interval between word lines is about 30 micrometers, if a high voltage (e.g., above 10V) is applied between a selected word line supplied with a program voltage and an unselected word line supplied with a pass voltage, a dielectric layer between the word lines can become broken down. This causes the pass and program voltages to be changed during a program operation. Accordingly, the reliability of the flash memory device is lowered.